The present disclosure relates to a memory device, and more particularly, to a calibration circuit having a stress applying mode and a memory device including the same.
In memory devices widely applied to high-performance electronic systems, a capacity and a speed have been increased. As an example of the memory devices, dynamic random access memories (DRAMs) are volatile memories and are memories where data is determined based on an electric charge stored in a capacitor.
A memory device may include an on-die termination (ODT) circuit and/or an off-chip driver (OCD) for preventing distortion of a signal transmitted between a memory controller and the memory device. A resistance (or impedance) of the ODT/OCD circuit is controlled by a control code generated by a calibration circuit. The calibration circuit performs a ZQ calibration operation of generating a pull-up control code and a pull-down control code which are converted based on conditions such as a process, a voltage, and a temperature (PVT).
The ODT/OCD circuit gets stressed in various forms depending on a memory operation, and in this case, the impedance matching characteristic of the ODT/OCD circuit is typically degraded, causing an increase in distortion of a signal. Thus, the calibration circuit may need to compensate the impedance matching characteristic of the ODT/OCD circuit.